ASIC Design
Power Mesh Compiler
Improving quality of place and route flow results by compiling intelligent power mesh which fits to the design best, care placement & routing resource to provide predictable and qualified solution.
Motivation
Our investigations on design without power mesh shows up to 45-50% less timing issues at placement optimization stage and much fewer shorts caused by congestion at routing stage in comparison to the design with conventional power mesh; this is what we call power mesh pressure.
Solution
softpowermesh compiler shrinks that pressure to 15-20% by increasing performance of place and route tool, which leads to better timing, congestion, power, and area results.
Results
Values & Features
Timing
Improve timing by reducing signal routing detours caused by power mesh
Shorten max displacement of standard cells after legalization
Congestion
Minimize the number of shorts by relaxing pressure on signal routing
Analytics
Explore physical design libraries and technology
Analyze routing and placement demands
softpower
Boost design quality with a combination of all merits on a single platform
Power
Reduce power consumption with efficient placement optimization ability
IR/EM
Straighten power mesh with respect to placement and switching activity.
Increase capacity of power mesh for better dynamic ir drop
Productivity
Decrease power mesh development effort
Shrink DRC and timing fix turnaround time
Industries
Data Center
IOT & IIOT
Automotive
Artificial Intelligence
Consumer Devices
Telecom & 5G
« Our solutions in your chip is another step to be a leader in your industry »
Interested in learning more?